1. Field of the Invention
The present invention relates to an image signal processing circuit and an image display apparatus. In particular, the present invention is preferable for application to an image signal processing circuit for displaying image data and a television signal on an image display apparatus, wherein the image data and the television signal are outputted from a computer.
2. Related Background Art
Heretofore, there are various types of images, which are displayed on an image display apparatus, such as a computer graphic, an image of a digital camera, and an image of a television signal. Then, there are a large number of formats of these images.
In an image display apparatus where formats of these images for display are fixed, it is possible to correspond to this format of image by selecting an image display apparatus fit to the image format. In a general-purpose image display apparatus, however, in order to display an image on the image display apparatus, it is necessary to give image processing to the image.
There exists IP conversion, frame rate conversion, resolution conversion, or the like representatively as image processing executed when displaying an image on this image display apparatus. The IP conversion among these converts an interlace signal like an NTSC signal of a television signal into a progressive signal. In addition, frame rate conversion is the conversion of a switching rate of a screen. Furthermore, the resolution conversion converts the number of horizontal pixel and vertical scanning lines.
When executing these types of image processing, the structure using frame memory is known. This frame memory stores image data for one screen, and reads the data as required for image processing. Then, it becomes possible to perform not only the image processing mentioned above but also to perform executing special image processing by adopting this frame memory.
Moreover, the technology of performing inversion, rotation, enlargement and shrinkage of an image is disclosed in Japanese Patent Application Laid-Open No. 1995-152905 by controlling the sequence of writing into or reading from frame memory.
In addition, generally, the multi-screen display which displays a plurality of screens on one image display apparatus has been performed in recent years. Then, with regard to this multi-screen display, methods of performing a multi-screen display by using a plurality of memory spaces are disclosed in Japanese Patent Application Laid-Open No. 1995-152905 and Japanese Patent Application Laid-Open No. 1999-296145.
Furthermore, Japanese Patent Application Laid-Open No. 2001-343966 discloses a method of image processing such as inversion and rotation by using a burst mode of SDRAM (Synchronous DRAM). This method aims at achieving the processing such as inversion and rotation by following method. An image data is divided into blocks, each of which is composed of predetermined numbers of pixels vertically and horizontally. The processing is performed such as inversion and rotation, and the like of data in a block by replacing the order of data in the block, performing burst transmission for every block. And the order of writing or reading of the block concerned is replaced.
By the way, when performing real-time processing using frame memory such as SDRAM, it is preferable to use a burst mode of SDRAM.
Then, as shown in FIG. 10, in this burst mode, it becomes possible continuously to perform data transfer using pipeline processing. An address count in the burst mode, however, becomes count-up in a sequential or interleaved mode. Hence, it is very hard to use the burst mode to the technology described in Japanese Patent Application Laid-Open No. 1995-152905 and Japanese Patent Application Laid-Open No. 1999-296145.
Specifically, in the methods described in Japanese Patent Application Laid-Open No. 1995-152905 and Japanese Patent Application Laid-Open No. 1999-296145, it is necessary to specify a row address and a column address for every access to memory. Furthermore, in moving image processing, it is necessary to enhance the processing speed of a memory access.